Serial FPDP Gen3 (sFPDP-Gen3) Core

Serial Front Panel Data Port Gen3 (Serial FPDP-Gen3) is a VITA standard (VITA 17.3-2018) serial communications protocol for use in high bandwidth systems.VITA/ANSI 17.3 is the successor to the ANSI/VITA 17.1 standard and supports the same user data frame types and sync methods, allowing for easy user upgrades from 17.1 to 17.3. ANSI/VITA 17.3 standard was designed to be lightweight and low latency by using the 64B/67B framing layer defined by the Interlaken v1.3 specification, providing over 95% bandwidth efficiency! Multi-lane channel bonding and automatic lane synchronization allow for unprecedented bandwidth scalability.

The primary benefits of sFPDP-Gen3 include:

  • Multi-lane channel bonding with advanced 64B/67B encoding
  • Support for all legacy FPDP data framing types and sync methods
  • New (optional) User Data Block (UDB) boundaries and per-UDB ID tags
  • Per-lane CRC32 protection for framing layer
  • CRC24 protection for all control words and UDB blocks
  • Local and remote UDB Acknowledge feature allows for guaranteed transmission schemes
  • Far-End link status information reports the health of the receive node
  • Automatic lane/bundle synchronization
  • Support for all transceiver line rates
  • Support for any number of bonded channels
  • Support for ALL transceiver-based FPGA device families

sFPDP Core Block Diagram

FPGA Device Support

In addition to the devices listed above, we’d be happy to add support for any transceiver based FPGA from Intel (previously Altera), Xilinx, or Microsemi at your request! New device families, reference designs, simulations, etc can be added to our standard install in as little as 3-5 days. This triple FPGA vendor support model gives our customers extra flexibility – don’t be limited by your interconnect IP! The sFPDP-Gen3 Core can be configured for ANY transceiver rate supported by the FPGA. This provides a scalable bandwidth solution for new products, and offers an attractive upgrade path for existing VITA 17.1 sFPDP systems, custom backplanes, and high-speed interconnects.

We currently have customers using our sFPDP Gen3 IP at rates ranging from single 2.5G channels up to 100G bonded channels. The 100G channels are implemented as 25Gx4 and have been hardware verified in the Stratix-10 GX H-Tile development kit as well as the Virtex UltraScale+ VCU118 development kit (example designs available). The ability to support multiple FPGA vendors at any line rate and any number of bonded channels makes the StreamDSP sFPDP Gen3 IP core one of the most flexible and scalable solutions available on the market today.

We are committed to strong customer support, and will make every effort to ensure a successful sFPDP-Gen3 integration. The FPGA IP core delivery includes a detailed User Guide, as well as “ready to run” demonstration designs for popular and easily available development boards. The demonstration designs include example single-lane and multi-lane transceiver configurations to make your integration easy. In addition to the demonstration designs, we provide a complete self-verifying simulation testbench with ready-to-run scripts.

sFPDP-Gen3 Datasheet

sFPDP-Gen3 Core Data Sheet

sFPDP-Gen3 User Guide

sFPDP-Gen3 Core User Guide

We support ALL device families to make integration as easy as possible for the user.

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